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To obtain the VHDL (or Verilog) source code described in this document, go to section VHDL (or Verilog) Code Download, page 3 for instructions. Introduction The Universal Asynchronous Receiver Transmitter (UART) is the most widely used serial data communication circuit ever.
A SPI receiver is written in VHDL and implemented on a CPLD as a SPI slave device. This allows the CPLD to act as an output expander, turning two SPI lines and a chip select line into eight output lines (8 digital outputs).SPI (Serial Peripheral Interface) is a four-wire synchronous serial bus. In this example, only three wires are used (data, clock and chip select) as data is only being received by the VHDL SPI receiver from a microcontroller (the micro is the SPI master).This is the first example of microcontroller to CPLD interfacing on this VHDL course so far. The microcontroller was previously only used to generate a clock pulse for the CPLD.This video shows the hardware, microcontroller software and VHDL code for this tutorial in action.
Asynchronous serial transmitter unit for the Icestick board, synthetized with Opensource Icestorm tools
- Baudrates: 300, 600, 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
- Clock frequency: 12Mhz
- Start bits: 1
- Data bits: 8
- Parity: None
- Stop bits: 1
- Description language: Verilog
- Toolchain: Opensource: Yosys, Arachne-pnr, Icestorm project
Serial packages consist of three parts: the start bit, the 8-bit data and the stop bit
Example of the serial transmission of the K character (ASCII 0x4B: Binary: 01001011)
The serial transmitter is encapsulated in the uart-tx entity
Ports
The transmitter unit has 4 inputs and 2 outputs:
- Inputs:
- clk: System clock (12MHz in the ICEstick board)
- rstn: Active low. When rstn is 0, the serial unit is reset (synchronous reset)
- start: Start the transmission. When it is a 1, the character from the input data is captured and the transmission begins
- data: 8-bit data to transmit
- Outputs:
- tx: Serial output. The data is sent as a serial package. It is connected to the transmission line
- ready: Transmitter status. When ready is 1, the unit is ready to transmit. A new character can be sent. when it is 0, the unit is busy transmitting the previous character.
Chronogram
The step for transmitting a character are the following:
- Wait until the ready signal is 1
- Place the character in the data input
- Set the start input to 1 (at least for 1 clock cycle)
After that, the unit clears the ready signal and start transmitting the character
![Uart verilog code explanation Uart verilog code explanation](/uploads/1/2/7/1/127152473/354003068.png)
Block diagram
The implementation of the transmitter is shown in the given block diagram
It consist of the following parts:
- Data register (8 bits): For storing the data to be sent
- Shift register (10 bits): For storing the serial package and sending its bits one by one. When the load signal is 1, it is loaded with a new character to transmit (8 bits). The two bits less significant are initialized with the binary value 01 (a start bit and a idle bit). When transmitting (load = 0), the less significant line is sent to the transmission line and then the register is shift right. A 1 is introduced in the most significant bit. It is only done when the clk_baud signal is 1. This signals determines the exact time when the next bit should be sent
- Baud generator: It generates a pulse of 1 cycle periodically, according to the baud rate configured
- Bit counter: It counts the bits that have already been transmitted. It only counts when load is 0
- controller: The finite state machine that generates the load and baudgen control signals for controlling the transmitter
- D flip-flops: There are two D flip-flops for registering both signals tx and start
Controller
The transmitter controller is a finite state machine with three states:
- IDLE: There is no transmission. The unit is not being used. The ready signal is 1. When the start signal is set to 1, it changes to the START state
- START: The transmission is started. The shift register is loaded with the data to be send (plus the start bit). The baud generator is started. After one clock cycle it automatically moves to the next state
- TRANS: Transmission state. The 10-bits serial packages is sent. When the bit counter is 11, it means that 10 bits have been already transmitted and the state changes to IDLE
This is a generic code for using the UART-tx in your designs in verilog. Of course, some details can change depending on the particular implementation (as for example the definitions of the wires)
![Vhdl Code For Serial Data Transmitters Vhdl Code For Serial Data Transmitters](/uploads/1/2/7/1/127152473/929388389.png)
Two examples in verilog on how to use the UART-tx unit are shown
txchar.v: Transmitting one character continuously
This is a hello world example. The UART-tx unit is instantiated and configured at 115200 baudrate. The character 'A' is wired to the data port and the signal start is set to 1, so that it will send the character 'A' continuously. The signal ready is NOT used (therefore it is not declared in the instantiation)
For simulating, execute the command:
The simulation in gtkwave is shown:
In total 3 characters 'A' are sent in simulation (there are 30 pulses in the clk_baud signal). The A character is 0x41 in hexadecimal and 01000001 in binary. The serial package is ten bits: the start bit (0) in the right and the stop bit (1) in the left. In binary it is: 1010000010It is transmitted in the reverse orden (first the less significant bit), so the bits that can be seen in the simulation are: 0100000101, repeated three times
For synthesizing the example, execute the following command:
The resources used by the example are:
Resource | used |
---|---|
PIOs | 5 / 96 |
PLBs | 12 / 160 |
BRAMs | 0 / 16 |
For uploading into the ICEstick execute:
For testing, launch the gtkterm application (or any other serial terminal program) and deactivate the DTR signal by pressing F7 (or the option control signals / toggle DTR from the menu bar). The Icestick starts to send the A character, filling the terminal completely.
tx-str.v: Transmitting a string
Example on how to transmit a string using the uart-tx unit. The reset is controlled by means of the DTR signal. Every time the circuit is reset, it sends the 'Hello!..' string and finish. A finite state machine is used to send the string
For simulating, execute the command:
The simulation in gtkwave is shown:
It can be seen that there are 8 pulses in the start signal (one per character sent). After the last character is sent (char_counter equal to 7) the fsm enters the last state (3) and finish
For synthesizing the example, execute the following command:
The resources used by the example are:
Resource | used |
---|---|
PIOs | 7 / 96 |
PLBs | 20 / 160 |
BRAMs | 0 / 16 |
For uploading into the ICEstick execute:
For testing, launch the gtkterm application (or any other serial terminal program) and deactivate the DTR signal by pressing F7 (or the option control signals / toggle DTR from the menu bar). The Icestick will send the string 'Hello!..'
The file baudgen.vh which contains the divisors for generating the standad baudrates, has been created using the baudgen.py python 3 script. Edit this file and change the clock frequency to adapt it to your own system clock
This is how it is used:
The python script is:
Juan González Gómez (Obijuan)
Licensed under a GPL v3 (code) and a Creative Commons Attribution-ShareAlike 4.0 International License (figures and images)
- Clifford Wolf, Mathias Lasser. Project IceStorm Thanks!
- Although this transmitter has been written from the scratch, it has been inspired by the one developed in the swapforth proyect by James Bowman. Thanks!
- BQ sponsored this project from 2015-07-01 to 2016-04-14. Thanks!
- Tutorial. Capítulo 24: Unidad de transmisión serie asíncrona (In spanish)
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